1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a power semiconductor device for driving high power. More specifically, the present invention relates to a structure for suppressing variations in saturation current in an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure.
2. Description of the Background Art
Power transistors are widely used for power conversion or control. One type of such power transistors is an insulated gate bipolar transistor (IGBT). The IGBT generally has an emitter layer of a first conductivity type, a base layer of a second conductivity type, a drift layer (base layer) of the first conductivity type, a collector layer of the second conductivity type, and a gate electrode formed facing the base layer and the drift layer with an insulating film interposed in between. A channel is formed in the base layer by applying a voltage to the gate electrode. Minority carriers (holes) are injected from the collector layer to the drift layer to cause conductivity modulation in the drift layer to reduce the resistance of the drift layer, and accordingly on-voltage upon conduction is reduced.
In such an IGBT, a trench IGBT having a gate electrode formed in a trench form is employed to reduce on-voltage and to reduce a chip area. An example of a configuration of such a trench IGBT is disclosed in Document 1 (Japanese Patent Laying-Open No. 2005-158850). Document 1 describes, as prior art thereof, a structure having an emitter region linearly formed in stripes to be orthogonal to a trench region, and discloses that the emitter region of such stripe form provides an effect as described below.
Specifically, Document 1 assumes a structure as described below as a starting structure of a trench gate IGBT. An emitter region is formed in a ladder form. This ladder-form emitter structure has an emitter region continuously extending along a side wall of the trench, and an emitter region of stripe form formed continuously and linearly with the emitter region formed on the side wall of an adjacent trench. In such ladder-shape emitter structure, a region in which a collector to emitter current flows is widened, and the saturation current is increased. In order to reduce the saturation current, the emitter region is simply formed in stripes to be orthogonal to the trench region.
Further, Document 1 develops the following arguments based on the finding that in order to reduce an on-voltage in the stripe-like emitter structure, it is necessary to set an area ratio between an area of the emitter region and an area of a channel P region (a base region disposed adjacent to the emitter region for making electrical contact with an emitter electrode) to an appropriate value. Specifically, when a surface area of the emitter region is preferentially determined to set the area ratio between the area of the emitter region and the area of the channel P region appropriately, a width of the emitter region formed on the side wall of the trench is determined according to its surface area, and saturation current cannot be adjusted. Conversely, when the width of the emitter region is preferentially determined to reduce the saturation current, the surface area of the emitter region is determined according to its width, and the area ratio between the area of the emitter region and the area of the channel P region cannot be adjusted. To solve such a trade-off problem, in Document 1, the emitter region is segmented along the trench region, and the width of the emitter region is made different for a contact region on the channel P region (base layer) and for the side wall of the trench. Thereby, the surface area of the emitter region is adjusted by adjusting one of the two widths of the emitter region, to reduce both saturation current and on-voltage concurrently.
Document 2 (Japanese Patent Laying-Open No. 2001-168333) discloses a structure for reducing transport current loss in a trench IGBT. In the structure described in Document 2, a dummy trench is provided in a region in which a P base layer and an emitter electrode are connected. With the dummy trench, an area of an ejection path for minority carriers (holes) ejected from the P base layer to the emitter electrode is reduced to increase the ejection resistance for reducing transport current loss. Specifically, with the dummy trench, an area of a current flowing path in an N-type drift layer is reduced, and thus a resistance of a path through which holes are ejected from the N-type drift layer (base layer) to the emitter electrode is increased. Thereby, holes are accumulated in an N-type base layer (drift layer) immediately below an effective trench gate serving as a gate. It is intended to increase a resistance against holes ejected to the emitter electrode and increase an amount of holes in the N-type drift layer, accordingly to increase an amount of electrons injected from the emitter electrode and increase injection efficiency of electrons, and thereby to reduce transport current loss.
When the emitter region is formed along the trench region as in the ladder-shape emitter structure as shown in Document 1, saturation current may possibly vary for each unit cell. Specifically, when forming a trench, firstly an emitter region is formed by impurity diffusion, and then the trench is formed. Therefore, when mask misalignment occurs between the trench and the emitter region, variations are caused in the length of the emitter layer and thus in the area of the emitter layer, and accordingly in the area of the region through which a collector to emitter current flows.
In contrast, when the emitter region is formed in stripes extending in a direction orthogonal to the trench, even if misalignment of a mask for the trench region occurs, the misalignment occurs in each trench at the same time, and thus variations in the stripe-like emitter region can be avoided. However, as discussed in Document 1, there is raised a trade-off problem concerning optimization of on-voltage and saturation current. Further, when the emitter region is formed in stripes, a problem described below is also raised, although it is not discussed in Document 1.
Specifically, when an IGBT is turned off, a collector current is cut off. In this operation, turn-off surge voltage is generated according to a current change rate di/dt due to an inductive load (including an interconnect). The surge voltage is added to collector to emitter voltage. When the emitter region is narrow in width, a large voltage is applied across a junction between the emitter and the base and breaks down the junction, which leads to element breakdown and raises a problem of narrowing an RBSOA (Reverse Bias Safe Operation Area). Conversely, when the emitter region is too wide, a base layer immediately below the emitter region becomes large in resistance. In this case, in an npnp parasitic thyristor formed of an emitter/base/drift layer (epitaxial layer)/collector layer, there arise a problem that latch-up occurs in which pn junction between the emitter and the base becomes conductive and the parasitic thyristor becomes conductive, leading to element breakdown or failure.
Although Document 1 described above considers the problem concerning the ratio between the surface area of the emitter region and the surface area of the base layer, it gives no consideration to the problem concerning the RBSOA when the stripe-like emitter region is employed.
Further, Document 2 describes that a dummy trench is provided to reduce an ejection area of holes, to increase a resistance of an ejection path for the holes for reducing transport current loss. However, although Document 2 shows, in FIG. 2 thereof, a structure having a trench formed in stripes, the emitter region in the structure is formed along the trench. Document 2 gives no consideration to the structure of the stripe-form emitter region formed in a direction orthogonal to the trench.